In a process to manufacture integrated circuits on a wafer (e.g., a substrate such as silicon, etc.), individual devices and/or circuits of the wafer are measured at different stages of the manufacturing process via wafer level testing. Generally, the wafer level testing monitors manufacturing processes, identifies process problems, and so forth. The integrated circuits of a wafer are also measured to determine if the integrated circuits are functional and will be further processed (e.g., packaged, etc.). In some examples, the integrated circuits are measured for one or more performance characteristics (e.g., threshold voltage, etc.). The results of the wafer level tests are recorded in a file correlating device location to device characteristics (e.g., a wafermap) and, during assembly of packaged integrated circuits, an automated die picker reads the file and selects integrated circuits to be packaged based on the results of the wafer level tests.
In general, to perform wafer level testing, a wafer prober having one or more wafer probes contacts with the wafer. The wafer probes have tips with thin diameters (e.g., 38 microns, etc.) and, as a result, wafer probe tips are susceptible to damage. In some examples, the wafer probe tips are not able to handle large amounts of current due to their diameter and may become damaged as a result of large amount of current. As a result, testing of high power devices, which are tested with significant currents, at the wafer level is often impossible to do using a continuous wave signal. Often, pulsed signals with a very low duty cycle (e.g., 10%) are used to test high power devices at the wafer level.